In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
The assignee of this invention has developed an event based test system wherein the desired test signals and strobe signals are produced by data from an event memory directly on a per pin basis. In an event based test system, test data is described in terms of event and its timing where events are any changes of the logic state in the signals used for testing a semiconductor device under test. For example, such changes are rising and falling of test signals (drive events) and strobe signals (strobe events or sampling events). Typically, a timing of each event is defined either as a time length from the most recent event (immediately prior to the current event) or in absolute time (from time zero) The present invention is directed to such an event based test system. With reference to FIGS. 1–3, the event based test system developed by the assignee of the invention is briefly described here. An example of basic structure in the event based test system is shown in a block diagram of FIG. 1.
In FIG. 1, the event based test system includes a host computer 12 and a bus interface 13 both are connected to a system bus 14, an internal bus 15, an address control logic 18, a failure memory 17, an event memory 30 consisting of an event count memory 20 and an event vernier memory 21, an event summing and scaling logic 22, an event generator 24, and a pin electronics 26. The event based test system evaluates a semiconductor device under test (DUT) 28 connected to the pin electronics 26.
An example of the host computer 12 is a work station having a UNIX operating system therein. The host computer 12 functions as a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and other test conditions, or to perform test result analysis in the host computer. The host computer 12 interfaces with a hardware test system through the system bus 14 and the bus interface 13.
The internal bus 15 is a bus in the hardware test system and is commonly connected to most of the functional blocks such as the address control logic 18, failure memory 17, event summing and scaling logic 22, and event generator 24. An example of the address control logic 18 is a tester processor which is exclusive to the hardware test system and is not accessible by a user. The tester processor (address control logic) 18 provides instructions to other functional blocks in the test system based on the test program and conditions from the host computer 12. The failure memory 17 stores test results, such as failure information of the DUT 28, in the addresses defined by the address control logic 18. The information stored in the failure memory 17 is used in the failure analysis stage of the device under test.
The address control logic 18 provides address data to the event count memory 20 and the event vernier memory 21 as shown in FIG. 1. In an actual test system, a plurality of sets of event count memory and event vernier memory will be provided, each set of which may correspond to a test pin of the test system. The event count and vernier memories store the timing data for each event of the test signals and strobe signals. The event count memory 20 stores the timing data which is an integer multiple of the reference clock (event count data), and the event vernier memory 21 stores timing data which is a fraction of the reference clock (event vernier data).
The event summing and scaling logic 22 is to produce data showing overall timing of each event based on the timing data from the event count memory 20 and the event vernier memory 21. Basically, such overall timing data is produced by summing the event count data (integer multiple data) and the event vernier data (the fractional data). During the process of summing the timing data, a carry over operation of the fractional data (offset to the integer data) is also conducted in the timing count and offset logic 22. Further during the process of producing the overall timing, timing data may be modified by a scaling factor so that the overall timing can be modified accordingly.
The event generator 24 is to actually generate the events based on the overall timing data from the event summing and scaling logic 22. The events (drive events and/or sampling signals) thus generated are provided to the DUT 28 through the pin electronics 26. Basically, the pin electronics 26 is formed of a large number of components, each of which includes a driver and a comparator as well as switches to establish input and output relationships with respect to the DUT 28.
For producing high resolution timings, as noted above, the time length (delay value) between the events is defined by a combination of an integer multiple of a reference clock cycle (event count data) and a fraction of the reference clock cycle (event vernier data). A timing relationship between the event count and the event vernier is shown in a timing chart of FIG. 2. In this example, a reference clock (event clock) of FIG. 2A has a clock cycle (time period) T. Event 0, Event 1 and Event 2 of FIG. 2C are related as to the timing in a manner shown in FIG. 2C. To describe Event 1 with reference to Event 0, the timing relationship of FIG. 2B is used in which NT denotes the event count which is N times of the reference clock period T and ΔT denotes the event vernier which is a fraction of the reference clock period T.
Each of these events may consist of a drive event or a sampling event. Drive events are those events where the signal on a tester pin is driven to a specific voltage level. In general, there are drive events specified to drive a pin of a device under test (DUT) to a logical high voltage level, a logical low voltage level, or to a high-impedance voltage level (drive Z). Sampling events are defined to be able to sample the output of the DUT pin at a logical high voltage level, a logical low voltage level, or an intermediate voltage level.
As noted above, in an event based test system, the event data in the event memory is expressed by a time difference between the current event and the previous event. Thus, to produce events according to the event data, an event based test system must be able to calculate the sum of the delays up to each event. This requires a logic in the test system to keep counting of the delay times expressed in the event count and to sum the event vernier values.
Such a relationship is shown in a timing chart of FIG. 3 in which Events 0–7 are expressed with reference to the reference clock having a time period T=1. For example, a time difference ΔV0 for Event 0 from a start point may be 0.75 (event count “0”, and event vernier “0.75”), and a time difference ΔV1 for Event 1 from Event 0 may be 1.50 (event count “1”, and event vernier “0.50”). In this situation, the total delay of Event 1 will be 2.25 where a logic in the test system counts two event clocks “2.0” and calculates the sum of event vernier “0.25” as the remaining fractional delay. This summing operation is essential for calculating the correct vernier during each event involved in a test signal.
In the U.S. Pat. No. 6,360,343, U.S. application Ser. No. 09/286,226 (now U.S. Pat. No. 6,557,133), and U.S. application Ser. No. 09/535,031 (now U.S. Pat. No. 6,668,331) owned by the same assignee of this invention, it is disclosed an event summing and scaling logic for calculating a timing of the current event using the event data from the event memory. These patents are incorporated by reference. The method described in the patents assumed direct match of both an event clock and a processing clock, i.e, the event count logic can simply count processing clocks and the vernier accumulation represents fractions of a processing clock cycle. Namely, the prior method does not take the difference between the event clock and the processing clock into account.
Within the context of the present invention, an event clock is a processing rate of the event data and a processing clock is a clock that the hardware uses to conduct its event processing. Typically, an event clock is the highest speed clock in the test system while a processing clock is a lower speed clock produced by dividing the frequency of the event clock to meet the operation speed of the hardware. Thus, in a high speed test system where hardware is able to operate in a high speed, the processing clock can be the same as the event clock. However, in a practical use, for a lower speed test system, an event clock is much faster than a processing clock and consequently, the method disclosed in the prior application cannot work effectively.
Therefore, what is needed is an event processing apparatus and method for a high speed event based test system which is able to perform high speed event timing processing even when a processing clock is much slower than an event clock.